1. Field of the Invention
The present invention relates to a semiconductor integrated circuit apparatus or more in particular to a semiconductor integrated circuit apparatus having a high speed and low power consumption at the same time.
2. Description of the Related Art
A CMOS circuit decreases in speed with a decrease in voltage. For the speed decrease to be complemented for, the threshold voltage of the MOS transistor (or the MIS transistor) is required to be reduced. The problem, however, is that the power consumption is increased by the subthreshold leakage current of the MOS transistor when the CMOS circuit is not in operation. A solution to this problem is described in IEEE Journal of Solid-State Circuits, Vol. 31, No. 11, November 1996, pp. 1770-1779 (hereinafter referred to as Reference 1).
The technique of Reference 1 is shown in FIG. 5. Reference characters vdd designate a power supply voltage which is 0.9 V in this prior art, vss the ground voltage, vbp is the substrate bias voltage of a PMOS, vbn the substrate bias voltage of a NMOS, numeral 200 a circuit configured with a MOS transistor, numeral 202 a substrate bias control circuit, and numeral 203 a mode signal. Generally, the potential difference between the voltage of the well or the substrate constituting the MOS transistor and the source voltage thereof is defined as the substrate bias. For our purpose, however, the absolute voltage (the potential difference with the ground voltage 0 V) of the well or the substrate constituting the MOS transistor is defined as the substrate bias.
In this conventional circuit, as the substrate bias of the MOS transistor constituting the CMOS circuit, a deeper voltage is applied when the CMOS circuit is not in operation (hereinafter referred to as the standby mode or standby state) than when the CMOS circuit is operating (hereinafter referred to as the active mode or the active state). The term xe2x80x9cdeeper substrate bias is appliedxe2x80x9d is defined as xe2x80x9ca higher voltage is applied for the PMOSxe2x80x9d and xe2x80x9ca lower voltage is applied for the NMOSxe2x80x9d. When xe2x80x9ca shallow substrate bias is appliedxe2x80x9d is said, on the other hand, it means that xe2x80x9ca lower voltage is applied for the PMOSxe2x80x9d and xe2x80x9ca higher voltage is applied for the NMOSxe2x80x9d. These expressions are used in the description that follows.
In the conventional circuit described in Reference 1, voltages of 1.4 V and xe2x88x920.5 V are applied as the substrate bias voltages of PMOS and NMOS in active mode, respectively, while 4.2 V and xe2x88x923.3 V are applied to the PMOS and NMOS as the substrate bias voltages thereof in standby mode. When a deep substrate bias is applied thereto, the MOS transistor exhibits a substrate bias effect in which the threshold voltage thereof increases. In standby mode, therefore, the subthreshold leakage current decreases than in active mode.
The reduction in power consumption in standby mode by use of the substrate bias in the conventional circuit has the following problems:
(1) Although the threshold voltage is changed in standby mode and active mode by the substrate bias effect, the dependence of the threshold voltage on the substrate bias generally decreases with the decrease in the gate length (Lg) of the MOS transistor.
(2) Generally, the CMOS circuit operates at higher speed with a smaller substrate bias effect, and therefore, designing a MOS transistor with an increased substrate bias effect in order to reduce the subthreshold leakage current in standby mode is conflicting.
(3) For the threshold voltage to change more between standby mode and active mode, a deeper substrate bias is applied. The application of a deeper substrate bias, however, causes a larger drain-well or wellxe2x80x94well potential difference of the MOS transistor, thereby leading to a larger junction leakage current in the PN junction.
The present inventors have discovered that once a substrate bias to some depth is applied to the a MOS transistor having a small gate oxide thickness (gate insulating film), the leakage current is not decreased even when a deeper substrate bias is applied thereto. Rather, a junction leakage current called the gate-induced drain leakage (GIDL) current comes to flow in the PN junction, often resulting in an increased leakage current for an increased power consumption in standby mode.
FIG. 19 is a diagram showing the gate voltage (Vgs) dependency of the drain current (Id) of the MOS transistor having a small gate oxide thickness. In a region with a large drain-gate voltage, the leakage current called the GIDL current flows from the drain to the substrate.
The curve A indicates the dependency characteristic in the case where the drain voltage (Vds) is 1.8 V and no substrate bias is applied (Vbb=0 V). The drain current (Id) with the gate voltage (Vgs) of 0 is the leakage current flowing while the transistor is in off state. The subthreshold leakage current flows in the case where Vgs is almost 0 V.
The curve B indicates the dependency characteristic in the case where Vds=1.8 V and a small amount of substrate bias is applied, e.g. in the case where a voltage Vbb of xe2x88x921.5 V is applied to the substrate. In this case, the substrate bias effect reduces the subthreshold leakage current. With the curve B, the magnitude of the leakage current flowing when the transistor is in off state is determined by the subthreshold leakage current.
The curve C indicates the dependency characteristic in the case where Vds is 1.8 V and the substrate bias is applied more deeply, for example, in the case where Vbb=xe2x88x922.3 V. In this case, the substrate bias effect reduces the subthreshold current on the one hand, while the GIDL current increases on the other hand. For the curve C, the GIDL current is a controlling leakage current flowing when the transistor is in off state. The application of a deeper substrate bias undesirably increases the leakage current with the transistor off as compared with when a shallower bias is applied (curve B).
In this way, with a MOS transistor having a small gate oxide thickness, it has been found that application of a substrate bias deeper than a predetermined level cannot reduce the leakage current but rather increases it due to the GIDL current against the past belief. Depending on the transistor profile (such as the impurities concentration of the diffusion layer), the GIDL current for the MOS transistor having a gate oxide thickness of not more than 5 nm increases to a non-negligible degree, and therefore the range of the substrate bias that can be applied is limited correspondingly. Thus, in the prior art, the effect of reducing the leakage current of the MOS transistor having a small gate oxide thickness is unavoidably limited.
(4) The subthreshold leakage current and the leakage current in the PN junction makes it difficult to conduct the IDDQ test for screening out defective products according to the current flowing in the circuit.
In a MOS transistor with a thin gate oxide having the gate voltage (Vgs) dependency of the drain current (Id) in off state as described above, the mere application of a deep substrate bias has no sufficient effect of reducing the leakage current. In FIG. 19, the curve D indicates the dependency characteristic in the case where a deep substrate bias is applied (Vbb=xe2x88x922.3 V) and the drain voltage (Vds=1.0 V) is further reduced. By decreasing the power supply voltage in this way, a deep substrate bias can be applied to the well while limiting the voltage applied between the diffusion layer and the well of the MOS transistor to a small value (3.3 V in this case). Further, the following characteristics are obtained.
(1) Since the electric field amount applied to the gate oxide film is so small that the GIDL current is reduced when Vgs is 0 V or thereabouts.
(2) With the decrease in drain voltage, the drain induced barrier lowering (DIBL) effect increases the threshold voltage of the MOS transistor. In this case, the substrate bias is applied and therefore the DIBL effect is enhanced. (In FIG. 19, comparison between curves C and D shows that the leakage current is generally smaller, the lower the voltage Vds.)
Utilizing this dependency characteristic, the leakage current can be remarkably reduced when a transistor having a thin gate oxide is in off state. For realizing these substrate bias conditions with each MOS transistor when the chip is in standby mode, the power supply voltage of the transistor is required to be reduced below a normal operation level to further deepen the substrate bias to be applied.
According to a method disclosed in JP-A-7-254685 laid open Oct. 3, 1995, the substrate bias voltage is controlled to reduce the subthreshold current by increasing the absolute value of the threshold level of the transistor in standby mode and at the same time, the power supply voltage of the transistor is reduced in order to reduce the gate leakage current and the bandxe2x80x94band tunnel leakage current. In this well-known method, however, each means involved is recognized to have an independent effect, but the fact fails to be recognized that these means have a synergistic effect of reducing the leakage current effectively in a thin-film transistor. Also, in the disclosed patent publication, an internal power supply voltage determined by the hot electron effect (Intvcc+xcex94) higher by xcex94 than the internal power supply voltage Intvcc for the other conventional methods is applied in active mode, while the internal power supply voltage is set to a value near VccMIN (Intvccxe2x88x92xcex94xe2x80x2) in standby mode. As a result, this circuit operates at higher speed than the other conventional circuits in active mode and decreases in power in standby mode. The only recognition in this method is that the scope of change (xcex94+xcex94xe2x80x2) of the internal power supply voltage is changed within the range of the operating power supply voltage of the internal circuit.
on the other hand, JP-A-10-229165 laid open Aug. 25, 1998, discloses a method in which both the substrate bias voltage and the power supply voltage are controlled in standby mode, so that the change rate of the substrate bias voltage is reduced for changing the threshold voltage. This conventional method also fails to recognize that the means mentioned above, when included in a thin-film transistor, have the synergistic effect of reducing the leakage current, but discloses a technique of changing the change amount by controlling the substrate bias voltage and the power supply voltage instead of by changing the substrate bias voltage alone.
In order to solve the problems described above, according to the present invention, there is provided a semiconductor integrated circuit apparatus comprising a first controlled circuit including at least a MOS transistor, and substrate bias control means for generating the substrate bias voltage of the MOS transistor, wherein the substrate bias control means is set in first mode thereby to allow a comparatively large current to flow between the drain and source of the MOS transistor while the substrate bias control means is set in second mode thereby to control the comparatively large current between the drain and the source of the MOS transistor to a smaller value, the first controlled circuit being impressed with a higher substrate bias voltage in second mode than in first mode for the PMOS transistor and impressed with a lower substrate bias voltage in second mode than in first mode for the NMOS transistor, the first controlled circuit being impressed with a lower power supply voltage in second mode than in first mode.
Further, a third mode is defined, and the substrate bias control means is set in second or third mode thereby to control the comparatively large current between the drain and source of the MOS transistor to a smaller value. In the process, the first controlled circuit is impressed with a higher substrate bias voltage in second and third modes than in first mode for the PMOS transistor and a lower substrate bias voltage in second and third modes than in first mode for the NMOS transistor.
A lower power supply voltage may be applied to the first controlled circuit in second mode than in first mode and the same power supply voltage may be applied to the first controlled circuit in third mode as in first mode.
According to another aspect of the invention, there is provided a semiconductor integrated circuit apparatus comprising a second controlled circuit and second power supply voltage control means for controlling the power supply voltage of the second controlled circuit, wherein in first mode, the second power supply voltage control means allows a comparatively large current to flow between the drain and source of the MOS transistor in the second controlled circuit, and in second mode, the second power supply voltage control means controls the comparatively large current between the drain and source of the MOS transistor in the second controlled circuit to a smaller value, the second controlled circuit being impressed with a lower power supply voltage in second mode than in first mode.
In the process, the substrate bias of the MOS transistor in the second controlled circuit may be controlled by the substrate bias control means to a voltage value higher in second and third modes than in first mode for the PMOS transistor and to a voltage value lower in second and third modes than in first mode for the NMOS transistor.
Also, the controlled circuit preferably includes a data path circuit wherein the data flow is preferably parallel between the data path circuit and the power net of the lowermost metal wire layer in the data path circuit of the power line controlled by the second power supply voltage control means.
In numerical terms, the threshold voltage of the MOS transistor constituting the first controlled circuit may be not more than 0.5 V, the power supply voltage of the first controlled circuit in second mode may be not more than 1.0 V but not less than 0.5 V, and the threshold voltage of the MOS transistor constituting the second controlled circuit may be not more than 0.5 V.
Further, the power line of the second controlled circuit controlled by the second power supply voltage control means is not more than 0.5 V in second mode. The power line of the second controlled circuit controlled by the second power supply voltage control means preferably has an impedance at least five times as large in second mode as in first mode.
According to still another aspect of the invention, there is provided a semiconductor integrated circuit apparatus comprising a controlled circuit including a MIS transistor, a first control circuit for controlling the substrate bias voltage of the MIS transistor, a second control circuit for controlling the power supply voltage of the MIS transistor, and mode signal input means for controlling the mode of the controlled circuit, wherein the first and second control circuits are controlled by one or a plurality of control signals formed based on the mode signal produced from the mode signal input means.
Also, the apparatus comprises a controlled circuit including a MIS transistor, a first control circuit for controlling the substrate bias voltage of the MIS transistor, and a second control circuit for controlling the drain-source voltage of the MIS transistor, wherein the first control circuit is set in first mode thereby to allow a comparatively large current to flow between the drain and source of a MOS transistor, the first control circuit is set in second mode thereby to control the comparatively large current between the drain and source of the MOS transistor to a smaller value, and the second control circuit controls the drain-source voltage of the MOS transistor to assume a low value at least during a part of the period when the first control circuit is set in second mode.
Also, from the viewpoint of wiring in the circuit, there is provided a semiconductor integrated circuit apparatus including a CMOS transistor circuit, first and second virtual power voltage lines connected to the source-drain circuit of the CMOS transistor, a first substrate bias line for controlling the substrate bias voltage of the PMOS transistor constituting the CMOS transistor circuit, a second substrate bias line for controlling the substrate bias voltage of the NMOS transistor constituting the CMOS transistor circuit, and a control circuit for controlling the potential difference between the first and second virtual power voltage lines downward while at the same time controlling the potential difference between the first and second substrate bias lines upward for a predetermined period of time.
In the process, the apparatus may comprise a first power supply voltage line connected to the first virtual power voltage line through a first switch and connected to the second virtual power voltage line through a third switch, and a second power voltage line connected to the second virtual power voltage line through a third switch and connected to the third substrate bias line through a fourth switch.
In a more specific layout, a switch cell including first to fourth switches and a plurality of cells including a CMOS transistor may be arranged along the first and second virtual power voltage lines and the first and second substrate bias voltage lines. At the same time, the first and second virtual power voltage lines and the first and second substrate bias voltage lines are arranged in parallel to each other, while the first and second power voltage lines are arranged in a position perpendicular thereto, and the switch cell can be arranged at a position nearer to the first and second power voltage lines than to the cells.
As another example, there is provided a semiconductor integrated circuit apparatus comprising a CMOS transistor circuit, first and second lines connected to the source-drain circuit of a CMOS transistor, a first substrate bias line for controlling the substrate bias voltage of the PMOS transistor constituting the CMOS transistor circuit, a second substrate bias line for controlling the substrate bias voltage of the NMOS transistor constituting the CMOS transistor, and a control circuit for controlling the potential difference between the first and second lines downward while at the same time controlling the potential difference between the first and second substrate bias lines upward for a predetermined period of time.
As still another example, there is provided a method of controlling a semiconductor integrated circuit apparatus comprising a MIS transistor, comprising the steps of performing a first operation for reducing the sub-threshold leakage current flowing between the drain and source of a MOS transistor by controlling the substrate bias voltage of a MIS transistor, and performing a second operation for reducing the drain-source voltage of the MIS transistor, wherein the period of the first operation is at least partially overlapped with the period of the second operation.
As a further developed example, there is provided a semiconductor integrated circuit apparatus comprising first and second circuit blocks including a CMOS transistor circuit, wherein each block includes first and second lines connected to the source-drain circuit of the CMOS transistor, a first substrate bias voltage line for controlling the substrate bias voltage of the PMOS transistor constituting the COMS transistor circuit, and a second substrate bias voltage line for controlling the substrate bias voltage of the NMOS transistor constituting the CMOS transistor, wherein the first circuit block is controlled for a predetermined period of time in such a manner that the voltage supplied to at least one of the first and second lines undergoes a change for predetermined period of time and the potential difference between the first and second substrate bias lines increases for a predetermined period of time, and the second circuit block interrupts the voltage supplied to at least one of the first and second lines for a predetermined period of time.